Digital Verification Engineer
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Job description
Company Description Mindlance is a national recruiting company which partners with many of the leading employers across the country. Feel free to check us out at http://www.mindlance.com. Job Description · 3years minimum experience and working knowledge of Object-Oriented SystemVerilog principles using UVM/OVM/VMM methodologies. · Extensive hand on experience in verifying digital blocks, building UVM based TB, writing UVM sequences, constraint-random testcases, using regModel (UVM_REG) API, drivers, monitors, scoreboard, functional coverage, assertions (SVA), simulations, regression, debug, bug reporting/tracking. · Experience in debugging RTL & Gate level simulations · Part of multiple tapeouts with high quality verification.
Qualifications
· Bachelor's, Electrical Engineering Preferred: Master's, Electrical Engineering or equivalent experience Additional Information To discuss on this opportunity feel free to reach Praveen and My Number is 732-630-6121 . Thanks